Si wafer dicing
2012: There is a new wafer dicing dystem at OSU - in the Dhagat/Jander lab in ECE. I think it is a Disco DAD 321 automatic dicer. http://www.disco.co.jp/eg/products/dicer/300.html
Email exchanges between Paul Newhouse and Chris Reidy, and Jack Rundel and Chris Reidy April 2011, describing wafer dicing. We will clean this up in time.
To Paul from Chris: I'm trying to figure out where you got some silicon substrates that I found. They are mounted in a circular metal frame, stuck on dicing tape. The wafer was cleaved into many 10*15mm dies, and they appear to have a thermal oxide layer on them that gives a purple color to them.
From Paul to Chris: Yes, what you have described are indeed Si/SiO2 wafers diced nicely into 10*15 mm substrates. These wafers were acquired from Hewlett Packard's site in town, since, at the time, Janet's group and Doug Keszler's group had a collaboration with the people out there and we could get substrates from them. You see, HP has (or had) a very nice dicing saw, allowing them to mount the wafers on plastic, and then dice them into those small 10 by 15's. The dicing saws are expensive and the cutting takes a skilled operator. In general, I usually got my diced wafers from Steven Meyers, Kai Jiang, or Jason Stowers (now all are employees of Inpria–ask Doug or Janet if you're not sure, but they still work on campus a lot). They usually had plenty of these diced wafers, and would let me have as many as I needed, sometimes in a 1“ by 1” size, too. We needed this particular size (10 by 15) to work with the device testing done by Wager's group in EE. They also fit a nice die that Ted Hinke (former machinist) made for me a few years ago (look for it around the labs, I can send you an image if you can't find it). This die holds the 10*15 wafer and has mounting pegs that locate channel and contact masks.
To summarize, first talk with Steve to see what he says. They might have some old ones laying around you can have. Also, I would inquire around campus–some faculty might have acquired a dicing saw recently, which would allow you to dice up wafters on campus (also ask Chris Tasker, a great equipment resource person–Janet knows who he is). All you would need to do is acquire some thermal oxide wafers, of which there should be tons, especially around the cleanroom in EE. Another option is UO. I imagine that between, OSU/UO/ONAMI someone has a dicing saw. Getting HP to do anything was always a bit of a pain, so I'd try all other options first. And by all means, use the ones you find around our labs.
From Chris to Jack: I'm a grad student working in Janet Tate's group at OSU, and I've recently come across some silicon substrates that were apparently prepared at HP. They are mounted in a circular metal frame, stuck on dicing tape. The wafer was cleaved into many 10*15mm dies with a dicing saw; if you could tell me anything about where they might have come from, who made them, or what I need to do to make my own, it would be very helpful.
To Chris from Jack: All I can help you with is making more. We scribe Si wafers with a UV laser. The kerf width is ~50um and there is a resulting debris field of loose silicon oxides that extends ~100um to either side. The cutting path is entirely up to you but should be rectilinear so as to align with the crystal grain.
We will need an index to charge to. If you plan on doing this quite a bit you should get badged and trained. Anything less than that I can do for you and you are welcome to join in the fun.
