Table of Contents

• P1 and P2 Ports
• Port Control and Data Registers
• Terminal Definitions

P1 and P2 Ports

• On the lower half of page 5 of the MSP4302x31 datasheet, the only IO capability of the MSP430g2231 is through the ports P1 (8 terminals) and P2 (2 terminals). The functions or signals available at these terminals are shown in Table 2 on page 6. P1.0-7 and P2.6-7 can be defined to provide digital input or output (IO). Also, they can be defined to provide specific internal digital signals, digital IO signals from another peripheral such as the universal serial interface (USI) or analog input channels for the ADC10, the 10-bit analog to digital converter peripheral.

Port Control and Data Registers

• To choose the signal to be applied to or read from a particular terminal, single bytes must be written to control registers. Refer to Table 12 in the datasheet on pages 14-15. For port P1, the control registers to be set first are P1SEL and P1DIR. These two control the direction of signal flow (in or out) and the choice of signal connected to the 8 individual terminals. The general description of these registers is given in section 8.2 beginning on page 336 of the family done.
• The data registers P1OUT and P1IN send and receive digital signals on specified terminals.

Terminal Definitions

• It is convenient to define the 1 condition for individual bits. Add these lines to the program before the main program:

        #define bit0 0x01   // 1
        #define bit1 0x02   // 2
        #define bit2 0x04   // 4
        #define bit3 0x08   // 8
        #define bit4 0x10   // 16
        #define bit5 0x20   // 32
        #define bit6 0x40   // 64
        #define bit7 0x80   // 128

• The direction registers PxDIR are used to specify individual bits for input or output. For input, the bit should be 0, and for output it should be 1. Define P1.0 and P1.4 as digital outputs by adding this statement to a program:

  P1DIR |= bit4 | bit0;              // Define P1.0 and P1.4 as outputs.

• The function select registers PxSEL and PxSEL2 are used to choose a signal function for each port from among the possibilities given the the data sheet. From Table 18 on page 37 of the datasheet, ACLK and SMCLK are possibilities for P1.0 and P1.4, respectively. ACLK is connected to P1.0 by setting bit 0 of P1SEL to 1. Terminals which are to be general purpose IO (GPIO) channels must have the corresponding bit in P1SEL be 0. SMCLK is connected to P1.4 by setting bit 4 of P1SEL to 1. Thus, add this line to a program:

  P1SEL = bit4 | bit0;   // Connect ACLK to P1.0 and SMCLK to P1.4,
                               // and set all other bits for digital I/O.

  Note that bits P1SEL.1-3 and P1SEL.5-7 are 0 as required for GPIO.