Table of Contents

• Clocks
• Observing the Default Clocks
• Specifying the Clocks

Clocks

• To use any MCU, you must understand the available clocks. This information is found in the "Clock Module" section 5.1 of the MSP430x2xx Family Users Guide. There are two internal oscillators, the digitally-controlled oscillator clock (DCOCLK) and the very low frequency oscillator clock (VLOCLK). There can be locations on the board for two other oscillators, a low frequency crystal oscillator (LFXT1CLK) and a high frequency crystal oscillator (XT2CLK). These four oscillator sources can be used to provide an array of clocks for the cpu and the peripherals as shown in Figure 5.1. The master clock (MCLK) is derived from any of the four oscillators, and it drives the cpu. The sub-main clock (SMCLK) is derived from any of the four oscillators, and it drives peripherals. The auxiliary clock (ACLK) is derived from either VLOCLK or LFXT1CLK, and it drives peripherals.

Observing the Default Clocks

• To view MCLK, SMCLK or ACLK, examine the pin definition table of the MSP4302x31 datasheet. SMCLK and ACLK are available, but MCLK is not.
• To determine the default settings for ACLK and SMCLK, these signals need to be routed to digital output pins, which are connected to bits of the digital I/O (DIO) ports P1 and P2. From the datasheet, ACLK can be directed to P1.0 and SMCLK can be directed to P1.4. The first step is to define P1.0 and P1.4 as digital outputs. Then ACLK and SMCLK will be connected to these outputs.
• It is convenient to define the 1 condition for individual bits. Add these lines to the program before the main program:

        #define bit0 0x01   // 1
        #define bit1 0x02   // 2
        #define bit2 0x04   // 4
        #define bit3 0x08   // 8
        #define bit4 0x10   // 16
        #define bit5 0x20   // 32
        #define bit6 0x40   // 64
        #define bit7 0x80   // 128

• The direction registers PxDIR are used to specify individual bits for input or output. For intput, the bit should be 0, and for output it should be 1. Define P1.0 and P1.4 as digital outputs by adding this statement to the original blinking program:

  P1DIR |= bit4 | bit0;              // Define P1.0 and P1.4 as outputs.

  The function select registers PxSEL and PxSEL2 are used to choose a signal function for each port from among the possibilities given the the data sheet. From Table 18 of the datasheet, ACLK is connected to P1.0 by setting bit 0 of P1SEL to 1. SMCLK is connected to P1.4 by setting bit 4 of P1SEL to 1. Thus, add this line to the program:

  P1SEL = bit4 | bit0;   // Connect ACLK to P1.0 and SMCLK to P1.4,
                               // and set all other bits for digital I/O.

  Assure that the blinking program does not conflict with these settings. Use P1.6 for blinking the green LED by adding these statements to the program:

  P1DIR |= bit6;   // Define P1.6 as output.

  Note that P1SEL.6 (bit 6 of P1SEL) is already 0 as required for digital I/O.
• Compile, load and execute and then obsere ACLK and SMCLK on P1.0 and P1.4, respectively.

Specifying the Clocks

• The DCO modulation is controlled by the MODx bits, which are bits 0-4 of DCOCTL, the DCO control register. Set them all to zero to turn off modulation. Refer to section 5.3.1 of the MSP430x2xx Family Users Guide.
• The DCO has 16 ranges defined by the RSELx bits, which are bits 0-3 of BCSCTL1, Basic Clock System Control Register 1. For the highest range, set RSELx = 15, i.e. all four bits high. Refer to section 5.3.2 of the family guide.
• Within a DCO range set by the RSELx bits, the DCOx bits select among 8 specific frequencies. The DCOx bits are bits 5-7 of DCOCTL. For the highest frequency, set DCOx = 7. Refer to section 5.3.1 of the family guide
• The MCU is specified to perform reliably when MCLK is 16 MHz. Set the clock control registers to achieve this condition. The clock control registers DCOCTL, BCSCTL1 and BCSCTL2 must be set.
  • According to the guide, DCOCTL has the default value of 0x60. A one byte number that sets the DCOx bits of DCOCTL to 7 and the lower 5 bits to 0 is 0xe0. The MODx bits of DCOCTL must be zero to defeat modulation, so a 1-byte number for this is 0x00. These two numbers could to be ORed in a bitwise sense to create DCOCTL. Add these lines to the program to configure DCOCTL:

          char DCOx = bit7 | bit6 | bit5;       // DCOx = 7
          char MODx = 0x00;                     // Set the MODx bits to 0.
          DCOCTL = DCOx | MODx;            // OR the two bytes bitwise.
          

  • BCSCTL1 has a default value 0x87. The RSELx bits (0-4) need to be set to 14. Bit 7 should be 1 to turn off the external high frequency oscillator input. Bit 6 should be 0 for low frequency mode on the external low frequency oscillator. Bits 4 and 5 are the DIVAx bits specifying the divider for ACLK. Set these to 0. Add these lines to the program to configure BCSCTL1:

          char DIVAx = 0x00;    /// bits 4-5 = low
          char XT2OFFx = bit7;   // bit 7 = 1
          char XTSx = 0x00;      // bit 6 = 0
          char RSELx = bit3 | bit2 | bit1; //| bit0;    // bits 3-1 = high
          BCSCTL1 = XT2OFFx | XTSx | DIVAx | RSELx;

    If you want to change any of these bits elsewhere in the program, then you must create a mask for the bits you do not wish to change. For example, to protect the DIVAx bits, define DIVAxMask = bit5 | bit4. Then, you can change RSELx bits with BCSCTL = BCSCTL AND DIVAxMask OR RSELx. Addition works here too: BCSCTL = (BCSCTL AND DIVAxMask) + RSELx.
  • BCSCTL2 has the default value 0. DCOR, the DCO resistor select bit, should be 0. This is bit 0 of BCSCTL2. SELS, the SMCLK source select bit, should be 0 to select DCOCLK as the source. This is bit 3 of BCSCTL2. DIVSx, the divider selection for SMCLK, comprises bits 1 and 2 of BCSCTL2, and they should be set to binary 00 for division by 1. SELMx, the MCLK source selection bits, should be set to binary 00 to select DCOCLK as the source. SELMX comprises bits 7 and 6 of BCSCTL2. DIVMx, the divider selection for MCLK, comprises bits 5 and 4 of BCSCTL2, and it should be set to binary 00 for division by 1. Add these lines to the program to configure BCSCTL2:

          char DCOR = 0x00;
          char SELSx =0x00;
          char DIVSx = 0x00;
          char SELMx = 0x00;
          char DIVMx = 0x00;
          BCSCTL2 = SELMx | DIVMx | SELSx | DIVSx | DCOR ;
          

  • BCSCTL3 seems irrelevant given the status of DCOCTL, BCSCTL1 and BCSCTL2. The default value is 0x05.
  • The remainder of the program is:

           for (;;)
           {
         	   volatile unsigned int i;            // volatile to prevent optimization
    	   P1OUT ^= bit6;                      // Toggle P1.6 using exclusive-OR
    	//i = 10000;                          // SW Delay
    	//do i--;
    	//while (i != 0);
           }
          

  • Compile, load and execute the program. With MLCK = 14/15 of maximum and SMCLK = MCLK, observe SMCLK with the oscilloscope on P1.4. Does the blinking program work at this speed?
  • The complete main.c.